ICS seminar: Prof. Jose Silva-Martinez

Posted on September 7, 2013

Location: ACES 2.402
Date:  September 19, 6:00 pm to 8:00 pm
Talk abstract:
Recent developments in mobile computing and wireless internet have led to exponential growth in demand for portable computers and smart phones equipped with WLAN operating at different standards. The digital computing required by these gadgets is facilitated by process scaling that follows Moore’s law and is expected to continue down to 10nm physical gate lengths. Various wireless standards have been developed over the years due to the high demand for faster data rate in portable wireless communications, which has pushed baseband bandwidths up to a few tens of MHz. When high-resolution continuous-time lowpass Σ? ADC architectures are selected for emerging products because of their efficiency, a wide bandwidth is essential in multi-standard applications to accommodate receiver bandwidth requirements. In this lecture, the fundamentals will be revised and limitations due to clock jitter and presence of strong blockers will be quantified; technology trends will be highlighted. A top-down design approach is followed, starting with system specifications down to design issues of main blocks. Properties of main architectures are fully described. Stability, linearity and power consumption issues in Σ? Modulators are addressed. Also, outof-band blocker effects on modulator’s SQNR and loop stability as well as loop saturation effects due to agile blockers, usually not properly discussed neither in books nor in scientific papers, are covered. Even though multi-bit architectures have been successfully utilized in multi-MHz bandwidth designs, significant research efforts are devoted to the find efficient solutions for the remaining issues: better linearity, wider bandwidth, robustness to clock jitter and co-existence with other standards. In particular, the feedback DAC nonlinearity significantly affects the ADC performance because it directly adds error to the filter input signal and it is not noise-shaped. The foundations on Σ? modulators will be covered first and then we will elaborate on linearity limitations as well as jitter and blocker tolerance issues. Two case studies experimentally verified are presented to illustrate design issues and to give insights into the possibilities that exist for solving these contemporary challenges with analog hardware and software-based processing techniques.
Speaker Bio:
Jose Silva-Martinez got his PhD degree from the Katholieke Universiteit Leuven, Belgium in 1992. He currently holds the rank of Texas Instruments Professor in Analog Engineering at the Department of ECE, Texas A&M University. Dr. Silva-Martinez is an IEEE-Fellow and member of the 2013-2014 CASS Distinguish Lecture Program. His record of publications show over 100 journals and 160 conferences, 2 books and 12 book chapters and 1 patent. He is co-author of the papers that received the 2011 Best Student Paper Award, IEEE MWCAS, the 2003 Best Student Paper Award, IEEE RF-IC, and recipient of the 1990 Best Paper Award, European Solid-State Circuits Conference (ESSCIRC). He got the 2005 Outstanding Professor Award by the ECE Department, Texas A&M University, 2005; co-Advised in Testing techniques the student who was Winner of the 2005 Best Doctoral Thesis Award, presented by the IEEE Test Technology Technical Council (TTTC), IEEE Computer Society.

ICS Seminar: Prof. Gabriel Rebeiz, IEEE Solid-State-Circuit-Society Distinguished Lecturer

Posted on April 6, 2013

Room location: ACES 2.302

Date:  April 18, 6:00 to 8:00 pm

Talk Abstract: This talk summarizes the recent work on phased arrays starting from the lower frequency chips at 6-12 GHz, and passing by the satellite communication chips at 6-22 GHz, and ending by the short-range communication chips and car radar chips at 60 GHz and 77-81 GHz. Different topologies will be covered: RF phase shifting, IF phase shifting, LO phase shifting, and and digital beamforming, with the pros and cons for each topology. Also, wafer-scale integration and the use of efficient on-chip antennas at 30 GHz and above will be presented. Phased-array systems from industry and academia will be covered in detail.

Biography:  Prof. Gabriel Rebeiz is the Wireless Communications Industry Chair Professor at the University of California, San Diego. He is an IEEE Fellow, an NSF Presidential Young Investigator, an URSI Koga Gold Medal Recipient, IEEE MTT 2003 Distinguished Young Engineer, and is the recipient of the IEEE MTT 2000 Microwave Prize, the IEEE MTT 2010 Distinguished Educator Award and the IEEE Antennas and Propagation 2011 John D. Kraus Antenna Award. He is also the recipient of the 1998 Amoco Teaching Award given to the best undergraduate teacher at the University of Michigan, and the 2008 Jacobs ECE Teacher of the Year Award at UCSD. His group has lead the development of complex RFICs for phased array applications from X-band to W-band, culminating recently in wafer-scale integration with high efficiency on-chip antennas. His phased array work is now used by most companies developing complex communication and radar systems. He has graduated 50 PhD students and 16 post-doctoral fellows, and currently leads a group of 20 PhD students in mm-wave RFIC, planar mm-wave antennas and terahertz systems, microwave circuits, RF MEMS, tunable networks, and is the Director of the UCSD/DARPA Center on RF MEMS Reliability and Design Fundamentals.

ICS Seminar: Prof. Jiang Hu

Posted on April 5, 2013

Date and time: Thursday, April 12, 2013, 2-3 p.m.
Location: ACES 2.402

Talk Title:

Voltage Adaptation for Power-Efficient Integrated Circuits

Abstract:

As people cram more and more functions into IC chips, the chip power density quickly approaches its fundamental limit. Power has surpassed performance and become the number one concern in many chip designs, from mobile to server applications. This talk will present some recent works on how to improve chip power efficiency at both architectural level and circuit level. At the architectural level, the power challenge is compounded by the increasingly large demand for on-chip communication bandwidth and data storage capacity. I will show how to efficiently monitor the performance of on-chip network and shared cache in chip multiprocessors. Dynamic voltage and frequency scaling control techniques for the shared resources will be described. At the circuit level, variability is another challenge that exacerbates the power problem. This talk will introduce a couple of voltage adaptation techniques that aim to harness the variability challenge in a power-efficient manner.

Speaker Bio:

Jiang Hu received the B. S. degree in optical engineering from Zhejiang University, China, in 1990, the M. S. degree in physics in 1997, and the Ph. D. degree in electrical engineering from the University of Minnesota in 2001. He was with IBM Microelectronics from January 2001 to June 2002. Currently, he is an associate professor in the Department of Electrical and Computer Engineering at the Texas A&M University. His research interest is on Computer-Aided Design for VLSI circuits and systems, especially on large scale circuit optimization, clock network synthesis, robust design and on-chip communication. He received a best paper award at the ACM/IEEE Design Automation Conference in 2001, an IBM Invention Achievement Award in 2003 and a best paper award at the IEEE/ACM International Conference on Computer-Aided Design in 2011. He has served as technical program committee member for DAC, ICCAD, ISPD, ISQED, ICCD, DATE, ASPDAC, ISLPED and ISCAS, technical program chair and general chair for the ACM International Symposium on Physical Design, and associated editor for IEEE Transactions on CAD and ACM Transactions on Design Automation of Electronic Systems.

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