ICS Seminar: Prof. Steven M. Nowick

Posted on March 24, 2013

Date and time: Monday, April 1, 2013, 3-4 p.m.
Location: ACES 2.402

Talk Title:

Designing a Low-Power and Low-Latency Network-on-Chip Switch Architecture for Cost-Effective GALS Multicore Systems


There has been a resurgence of interest in asynchronous (i.e. clockless) digital design in recent years, as designers confront formidable challenges of high-speed clock distribution, chip complexity, power, design time, mixed-timing domains and reusability.

This talk is in two parts.  First, I will give a brief overview of asynchronous and GALS (globally-asynchronous locally-synchronous) design, including a basic technical introduction and highlights of recent industry activity (Fulcrum Microsystems [now part of Intel], Boeing, Sun, Philips) and academia. I will also survey some of my key research areas:  (i) robust mixed-timing interfaces, (ii) low-power delay-insensitive codes for global communication, and (iii) ultra-low energy systems (subthreshold/near-threshold).

In the second part, I will introduce our recent asynchronous switch design for very low-overhead GALS interconnection networks. Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems. However, they have found only limited applicability so far due to two main reasons:  the lack of proper design tool flows as well as their significant area footprint over their synchronous counterparts. This talk proposes a largely unexplored design point for asynchronous NoCs, relying on transition-signaling (i.e. 2-phase handshaking) and single-rail bundled data encoding, which contributes to break the above barriers.

Compared to a leading lightweight synchronous switch architecture, “xpipesLite,” the post-layout asynchronous switch achieved a 71% area reduction, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit. A semi-automated CAD tool flow was developed, using Synopsys Design Compiler and IC Compiler.

This is joint work with Davide Bertozzi and Alberto Ghiribaldi (University of Ferrara, Italy).

Speaker Bio:

STEVEN M. NOWICK is a Professor of Computer Science and Electrical Engineering at Columbia University, and Chair of the Computer Engineering Program. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University.   His main research area is on design methodologies and CAD tools for synthesis and optimization of asynchronous and mixed-timing digital systems.  His current projects include:  scalable networks-on-chip (NoC’s) for shared-memory parallel processors and embedded systems, ultra-low energy digital systems, and low-power and robust global communication.

Dr. Nowick is an IEEE Fellow (2009), and a recipient of an Alfred P. Sloan Research Fellowship (1995), and NSF CAREER (1995) and RIA (1993) Awards. He received Best Paper Awards at the  International Conference on Computer Design (1991, 2012) and the IEEE Async Symposium (2000). He co-founded the IEEE “Async” Symposia series, and served as Program Committee Co-Chair (1994, 1999) and General Co-Chair (2005). He was Program Chair of the IEEE/ACM International Workshop on Logic and Synthesis (2002), and program track/subcommittee chair at DAC (2011-13), DATE (2009-10) and ICCD (2005). He is currently associate editor ACM Journal on Emerging Technologies in Computer Systems (JETC), and formerly associate editor of IEEE Transactions on CAD and IEEE Transactions on VLSI Systems.  He is also currently the selection committee chair of the ACM/SIGDA Outstanding Dissertation in EDA (OPDA) Award (2012-13).  He received the Columbia Engineering School (SEAS) Alumni Distinguished Faculty Teaching Award (2010).  He holds 11 issued US patents.