ICS Seminar: Dr. Milos Krstic, POB 2.402, May 7, 4-5pm

Posted on April 14, 2015

Title: Overview of the Methods for Design of Application Specific Integrated Circuits (ASICs) Explored at the IHP Institute at Frankfurt (Oder), Germany

Research institute IHP – Innovation for High Performance Microelectronics performs the cutting edge research activities in the area of high frequency integrated circuits. Based on its internal BiCMOS technology with high performance bipolar transistors (fmax=500 GHz) the main topic is the development of wireless communication systems for telecommunications, aerospace, medicine, and automation. In the latest years, following the strategy More than Moore, several additional research directions have been established including graphene transistor development, microfluidics, RF MEMS, integrated BiMCOS-Silicon Photonics process, Terahertz electronics, high performance broadband networks, ultra-low power sensor networks etc.

In this talk an overview of the various research activities at IHP will be provided. The main focus will be on the activities of ASIC design and test method group at IHP. The focus of this group are the innovative design methods for low-power, low-noise, and fault tolerant ASICs. One of the major topics is asynchronous and globally asynchronous locally synchronous (GALS) circuit design. This talk will disclose low-EMI features of GALS technique, which are extremely important for complex implementations in scaled technologies and mixed SoC designs. The achieved results measured on complex CMOS chip named Moonrake in the scaled 40 nm CMOS process showed that EMI reduction of up to 26 dB could be achieved using GALS technology. With respect to fault tolerant design techniques, the main focus was on adaptive multi-core processor development for space. With the active hardware support several modes of operation of the multi-core system have been enabled, including fault tolerant and lifetime extension mode. The demonstrator chip has been implemented, integrating 8-core system, and recently successfully tested.

Milos Krstic received his M.Sc. degree in Electrical Engineering at Faculty of Electronic Eng. Nis, Serbia in 2001, and his Dr.-Ing. degree from the Brandenburg University of Technology, Cottbus, Germany in 2006. Since 2001 he has been with IHP Microelectronics, Frankfurt (Oder), Germany, in the Wireless Communication Systems Department. For the last few years, his work was mainly focused on digital design techniques for wireless applications, fault tolerant ASIC design, and globally-asynchronous locally-synchronous (GALS) methodologies for digital systems integration. Since 2010 he is leading the group for Design & Test methodology that includes 15 researchers and test engineers. He was coordinating EU project GALAXY on GALS methodology for system integration, and now leads various projects in the area of GALS design, switching noise reduction techniques, radhard and fault tolerant design for space applications. His academic and professional work was followed with more than 90 journal and conference papers and 11 submitted patent applications (7 registered patents).