ICS Seminar: Prof. Shanthi Pavan

Posted on February 15, 2013

Location: ENS 314

Date and time: 5pm, Friday, March 1st

Topic: Continuous-time Delta Sigma Modulators with Improved Linearity and Reduced Clock Jitter Sensitivity

Conventional continuous-time modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to inter-symbol-interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. Measured results from a test chip fabricated in 0.18um CMOS demonstrate the efficacy of the SCRZ technique.


Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the  Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D  degrees from Columbia University, New York in 1997 and 1999 respectively. After working in industry  for a few years, he moved to  the Indian Institute of Technology-Madras, where he is now a  Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit  design, sensing and signal processing.  Dr.Pavan is the recipient of several awards, including the IEEE  Circuits and Systems Society Darlington Best Paper Award (2009). He is the Deputy Editor in Chief of the  IEEE Transactions on Circuits and  Systems: Part I – Regular Papers and serves on the Data Converter  Committee of the International Solid State Circuits Conference (ISSCC).