Integrated Circuits and Systems Group

Date and time: Monday, April 1, 2013, 3-4 p.m.
Location: ACES 2.402

Talk Title:

Designing a Low-Power and Low-Latency Network-on-Chip Switch Architecture for Cost-Effective GALS Multicore Systems

Abstract:

There has been a resurgence of interest in asynchronous (i.e. clockless) digital design in recent years, as designers confront formidable challenges of high-speed clock distribution, chip complexity, power, design time, mixed-timing domains and reusability.

This talk is in two parts.  First, I will give a brief overview of asynchronous and GALS (globally-asynchronous locally-synchronous) design, including a basic technical introduction and highlights of recent industry activity (Fulcrum Microsystems [now part of Intel], Boeing, Sun, Philips) and academia. I will also survey some of my key research areas:  (i) robust mixed-timing interfaces, (ii) low-power delay-insensitive codes for global communication, and (iii) ultra-low energy systems (subthreshold/near-threshold).

In the second part, I will introduce our recent asynchronous switch design for very low-overhead GALS interconnection networks. Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems. However, they have found only limited applicability so far due to two main reasons:  the lack of proper design tool flows as well as their significant area footprint over their synchronous counterparts. This talk proposes a largely unexplored design point for asynchronous NoCs, relying on transition-signaling (i.e. 2-phase handshaking) and single-rail bundled data encoding, which contributes to break the above barriers.

Compared to a leading lightweight synchronous switch architecture, “xpipesLite,” the post-layout asynchronous switch achieved a 71% area reduction, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit. A semi-automated CAD tool flow was developed, using Synopsys Design Compiler and IC Compiler.

This is joint work with Davide Bertozzi and Alberto Ghiribaldi (University of Ferrara, Italy).

Speaker Bio:

STEVEN M. NOWICK is a Professor of Computer Science and Electrical Engineering at Columbia University, and Chair of the Computer Engineering Program. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University.   His main research area is on design methodologies and CAD tools for synthesis and optimization of asynchronous and mixed-timing digital systems.  His current projects include:  scalable networks-on-chip (NoC’s) for shared-memory parallel processors and embedded systems, ultra-low energy digital systems, and low-power and robust global communication.

Dr. Nowick is an IEEE Fellow (2009), and a recipient of an Alfred P. Sloan Research Fellowship (1995), and NSF CAREER (1995) and RIA (1993) Awards. He received Best Paper Awards at the  International Conference on Computer Design (1991, 2012) and the IEEE Async Symposium (2000). He co-founded the IEEE “Async” Symposia series, and served as Program Committee Co-Chair (1994, 1999) and General Co-Chair (2005). He was Program Chair of the IEEE/ACM International Workshop on Logic and Synthesis (2002), and program track/subcommittee chair at DAC (2011-13), DATE (2009-10) and ICCD (2005). He is currently associate editor ACM Journal on Emerging Technologies in Computer Systems (JETC), and formerly associate editor of IEEE Transactions on CAD and IEEE Transactions on VLSI Systems.  He is also currently the selection committee chair of the ACM/SIGDA Outstanding Dissertation in EDA (OPDA) Award (2012-13).  He received the Columbia Engineering School (SEAS) Alumni Distinguished Faculty Teaching Award (2010).  He holds 11 issued US patents.

Location: ENS 314

Date and time: 2pm, Tuesday, Feb. 26th

Talk Title:

Magnetic Resonance of Porous Media

Abstract:

NMR has become an important technique for characterization of porous materials in recent years. In particular, its importance in petroleum exploration has been increased by the recent progress in NMR well-logging. The continuous rise of global demand for energy and the difficulty of significantly increasing production capacity demands better evaluation of oil reservoirs. This talk will outline the challenges in our ability to understand rock structures and fluid composition in oil and gas reservoirs, and the MR technical development and their applications. These new applications demands a new type of NMR system that is capable of broadband RF transmission and reception  I will also discuss a new concept of NMR system with a fully broadband front-end electronics. This change to the MR front-end electronics enables a fully digital MR system with unparalleled flexibility and simplicity for multi-frequency MR, a transition analogous to the one from classic analog radios to modern digital receivers found in mobile electronics.

Speaker Bio:

Dr. Yiqiao Song is currently a Scientific Advisor at Schlumberger-Doll Research. He earned his BS from Peking University and Ph.D. from Northwestern University. He worked in UC Berkeley as a Miller Research Fellow before joining Schlumberger in 1997. His focus has been developing NMR/MRI/NQR methodologies and instrumentation for well-logging,  understanding materials including porous media (rocks, cements and composites), complex fluids (crude oils, emulsion, mixtures) and biological materials. He is also affiliated part-time at Massachusetts General Hospital to study complex tissue structures. He was elected Fellow of American Physical Society in 2009 and to the Editorial board of Journal of Magnetic Resonance. Dr. Song has published over 100 papers in scientific journals and awarded over 20 patents.

Location: ENS 314

Date and time: 5pm, Friday, March 1st

Topic: Continuous-time Delta Sigma Modulators with Improved Linearity and Reduced Clock Jitter Sensitivity

Conventional continuous-time modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to inter-symbol-interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. Measured results from a test chip fabricated in 0.18um CMOS demonstrate the efficacy of the SCRZ technique.

Biography:

Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the  Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D  degrees from Columbia University, New York in 1997 and 1999 respectively. After working in industry  for a few years, he moved to  the Indian Institute of Technology-Madras, where he is now a  Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit  design, sensing and signal processing.  Dr.Pavan is the recipient of several awards, including the IEEE  Circuits and Systems Society Darlington Best Paper Award (2009). He is the Deputy Editor in Chief of the  IEEE Transactions on Circuits and  Systems: Part I – Regular Papers and serves on the Data Converter  Committee of the International Solid State Circuits Conference (ISSCC).