ICS Seminar: Prof. Aviral Shrivastava from ASU

Posted on February 26, 2014

Date and time: March 5, 4pm
Location: POB 2.402

Title: Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors

Abstract: Control Flow Checking (CFC) based techniques have gained a
reputation of providing effective, yet low-overhead protection from
soft errors. The basic idea is that if the control flow – or the
sequence of instructions that are executed – is correct, then most
probably the execution of the program is correct. Although researchers
claim the effectiveness of the proposed CFC techniques, we argue that
their evaluation has been inadequate and even wrong! Recently, the
metric of vulnerability has been proposed to quantify the
susceptibility of computation to soft errors. Laced with this
comprehensive metric, we quantitatively evaluate the effectiveness of
several existing CFC schemes, and obtain surprising results. Our
results show that existing CFC techniques are not only ineffective in
protecting from soft errors, but that they incur additional power and
performance overheads. Software-only CFC protection schemes (CFCSS
[21], CFCSS+NA [5], and CEDA [26]) increase system vulnerability by
18% to 21% with 17% to 38% performance overhead; hybrid CFC protection
technique, CFEDC [7] increases the vulnerability by 5%; while the
vulnerability remains almost the same for hardware only CFC protection
technique, CFCET [22], but they cause overheads of design cost, area,
and power due to the hardware modifications required for their

Bio: Aviral Shrivastava is Associate Professor in the School of
Computing,Informatics and Decision Systems Engineering at the Arizona
State University, where he has established and heads the Compiler and
Microarchitecture Labs (CML). He received his Ph.D. and Masters in
Information and Computer Science from University of California,
Irvine, and bachelors in Computer Science and Engineering from Indian
Institute of Technology, Delhi. He is recipient of the 2011 NSF CAREER
Award, and 2012 Outstanding Junior Researcher in the School of
Computing, Informatics, and Decision Systems Engineering. His research
focuses in three important directions, 1. Manycore architectures and
compilers, 2. Programmable accelerators and compilers, and 3.
Quantitative Resilience. His research is funded by DOE, NSF and
several industries including Intel, Nvidia, Microsoft, Raytheon
Missile Systems, Samsung etc. He serves on organizing and program
committees of several premier embedded system conferences, including
review panels.

ICS Seminar: Prof. Ayse Coskun from Boston University

Posted on February 3, 2014

Date: Feb. 10, 4-5pm
Location: ENS 314
Talk abstract:
Energy efficiency is a central issue in all computing domains. In data
centers, operational and cooling costs impose significant sustainability
challenges. In tandem, future processors are expected to run complex,
highly performance demanding workloads, making the well-studied energy
management policies inadequate. High power densities also increase the
on-chip temperatures and thermal variations, both of which degrade
system reliability and add to the system design complexity. Achieving
orders of magnitude of energy efficiency improvements requires novel
system and software design approaches coupled with dynamic techniques
that recognize the hardware-software characteristics and understand the
complex interplay among performance, energy, and temperature. This talk
will discuss two closely-tied research thrusts: (1) designing novel 3D
stacked architectures and the necessary runtime management strategies
for improving processor energy efficiency; and (2) developing workload
management and power regulation methods in data centers to reduce the
overall energy cost of computing.
Speaker Bio:
Ayse K. Coskun is an assistant professor in the Electrical and Computer
Engineering Department at Boston University. She received her MS and PhD
degrees in Computer Science and Engineering from University of
California, San Diego. Coskun’s research interests are temperature and
energy management, 3D stack architectures, computer architecture,
embedded systems, and data center energy efficiency. Prof. Coskun worked
at Sun Microsystems (now Oracle), San Diego prior to her current
position at BU. She received the best paper award at IFIP/IEEE VLSI-SoC
Conference in 2009 and at High Performance Embedded Computing (HPEC)
Workshop in 2011, and she is a recipient of the NSF CAREER award. She
has served as an associate editor for ACM Transactions on Design
Automation of Electronic Systems and IEEE Embedded Systems Letters.
Coskun also writes a bi-monthly column on green computing for Circuit
Cellar magazine.

ICS Seminar: Prof. Vladimir Stojanovic from UC Berkeley

Posted on November 8, 2013

Building: UT Austin POB(ACES) 2.402
Room Number: 2.402
201 East 24th St
Austin,  Texas
United States 78712

Date:  November 14, 6:00 pm to 8:00 pm

Abstract: Chip design is radically changing. This period of change is
a very exciting time in integrated circuit and system design. On one
hand, cross-layer design approaches need to be invented to improve
system performance despite CMOS scaling slowdown. On the other, a
variety of emerging devices are lined-up to extend or potentially
surpass the capabilities of CMOS technology, but require key
innovations at the integration, circuits and system levels. This
lecture describes how monolithic integration of photonic links can
revolutionize the VLSI chip design, dramatically improving its
performance and energy-efficiency. Limited scaling of both on-chip and
off-chip interconnects, coupled with CMOS scaling slowdown have led to
energy-efficiency and bandwidth density constraints that are emerging
fast as the major performance bottlenecks in embedded and
high-performance digital systems. While optical interconnects have
shown promise in extensive architectural studies to date, significant
challenges need to be overcome both in device and circuit design as
well as the integration strategy. We illustrate how our cross-layer
approach guides the system design by connecting process, device and
circuit optimizations to system-level metrics, exposing the inherent
trade-offs and design sensitivities. Our experimental platforms
demonstrate the technology potential at the system level and provide
feedback to modeling and device design. In particular, we’ll describe
the recent breakthroughs in monolithic photonic memory interface
platform with fastest and most energy-efficient modulators
demonstrated in a 45nm process node. Based on these design principles
and technology demonstrations, we project that in the next decade
tailored hybrid (electrical/optical) integrated systems will provide
orders of magnitude performance improvements at the system level and
revolutionize the way we build future VLSI systems. Moreover, just
like integrating the inductor into CMOS at the end of 1990s
revolutionized the RF design and enabled mobile revolution,
integration of silicon-photonic active and passive devices with CMOS
is greatly positioned to revolutionize a number of analog and
mixed-signal applications – low-phase noise signal sources and large
bandwidth, high-resolution ADCs, to name a few.

Bio: Vladimir Stojanovic is an Associate Professor of Electrical
Engineering and Computer Science at University of California,
Berkeley. His research interests include design, modeling and
optimization of integrated systems, from CMOS-based VLSI blocks and
interfaces to system design with emerging devices like NEM relays and
silicon-photonics. He is also interested in design and implementation
of energy-efficient electrical and optical networks, and digital
communication techniques in high-speed interfaces and high-speed
mixed-signal IC design. Vladimir received his Ph.D. in Electrical
Engineering from Stanford University in 2005, and the Dipl. Ing.
degree from the University of Belgrade, Serbia in 1998. He was also
with Rambus, Inc., Los Altos, CA, from 2001 through 2004 and with MIT
as Associate Professor from 2005-2013. He received the 2006 IBM
Faculty Partnership Award, and the 2009 NSF CAREER Award as well as
the 2008 ICCAD William J. McCalla, 2008 IEEE Transactions on Advanced
Packaging, and 2010 ISSCC Jack Raper best paper awards. He is an IEEE
Solid-State Circuits Society Distinguished Lecturer for the 2012-2013

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