ICS Seminar: Prof. Aviral Shrivastava from ASU
Date and time: March 5, 4pm
Location: POB 2.402
Title: Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors
Abstract: Control Flow Checking (CFC) based techniques have gained a
reputation of providing effective, yet low-overhead protection from
soft errors. The basic idea is that if the control flow – or the
sequence of instructions that are executed – is correct, then most
probably the execution of the program is correct. Although researchers
claim the effectiveness of the proposed CFC techniques, we argue that
their evaluation has been inadequate and even wrong! Recently, the
metric of vulnerability has been proposed to quantify the
susceptibility of computation to soft errors. Laced with this
comprehensive metric, we quantitatively evaluate the effectiveness of
several existing CFC schemes, and obtain surprising results. Our
results show that existing CFC techniques are not only ineffective in
protecting from soft errors, but that they incur additional power and
performance overheads. Software-only CFC protection schemes (CFCSS
[21], CFCSS+NA [5], and CEDA [26]) increase system vulnerability by
18% to 21% with 17% to 38% performance overhead; hybrid CFC protection
technique, CFEDC [7] increases the vulnerability by 5%; while the
vulnerability remains almost the same for hardware only CFC protection
technique, CFCET [22], but they cause overheads of design cost, area,
and power due to the hardware modifications required for their
implementations.
Bio: Aviral Shrivastava is Associate Professor in the School of
Computing,Informatics and Decision Systems Engineering at the Arizona
State University, where he has established and heads the Compiler and
Microarchitecture Labs (CML). He received his Ph.D. and Masters in
Information and Computer Science from University of California,
Irvine, and bachelors in Computer Science and Engineering from Indian
Institute of Technology, Delhi. He is recipient of the 2011 NSF CAREER
Award, and 2012 Outstanding Junior Researcher in the School of
Computing, Informatics, and Decision Systems Engineering. His research
focuses in three important directions, 1. Manycore architectures and
compilers, 2. Programmable accelerators and compilers, and 3.
Quantitative Resilience. His research is funded by DOE, NSF and
several industries including Intel, Nvidia, Microsoft, Raytheon
Missile Systems, Samsung etc. He serves on organizing and program
committees of several premier embedded system conferences, including
DAC, ICCAD, ISLPED, CODES+ISSS, CASES and LCTES, and NSF and DOE
review panels.