ICS Seminar: Prof. Gabor Temes, OSU, Mon, Oct. 19, POB 2.402, 6pm

Posted on September 4, 2015

Date: Mon, Oct. 19, 2015

Time: 6-8pm

Place: POB 2.402


Talk abstract: Integrated sensor interfaces need high-resolution and power-efficient data converters. In some applications, a single A/D converter has to be multiplexed between many sensors. Often, the optimum choice for the ADC architecture is the incremental data converter (IDC). An IDC is a memory-less (Nyquist-rate) ADC, which uses an embedded delta-sigma (ΔΣ) ADC and a digital postfilter to achieve very high accuracy (say, 22 ENOB) through noise shaping. As in a ΔΣ ADC, the accuracy can be enhanced by cascading several ADC stages to achieve noise cancellation. The resulting extended counting ADC (EDC) may share the hardware between several stages.

In this seminar, a tutorial introduction will be given which explains the peculiar features of IDCs and EDCs, as well as the relative merits and limitations of IDCs vs. conventional Nyquist-rate ADCs and ΔΣ ADCs. After that, our recent research results on the design of micro-power IDCs and EDCs will be discussed, and illustrated with implemented data converters.

Speaker bio: Gabor C. Temes is a Life Fellow of IEEE. He published over 600 research papers, and wrote or coauthored five books on circuit design, translated into Chinese, Japanese, Russian and other languages. He holds 15 patents on novel circuits and devices. He served as Editor of IEEE TCAS-I. He received the CAS Darlington Award, and the CAS Education as well as Technical Achievement Awards. He won the 1998 IEEE Graduate Teaching Award, the 2006 IEEE Gustav Robert Kirchhoff Award, and the 2009 CAS Mac Van Valkenburg Award. He is a member of the U.S. National Academy of Engineering.