ICS Seminar: Prof. Hashomito
Prof. Masanori Hashimoto
Osaka University, Osaka, Japan
Thursday, Sep. 1st, 3:00pm – 5:00pm
Adaptive Performance Compensation with On-Chip Variation Monitoring
This talk discusses adaptive performance control with two types of on-chip variation sensors. The first sensor gives estimates of die-to-die and spatially correlated variations that are decomposed into NMOS/PMOS threshold voltages and channel lengths. As a potential performance control with this type of sensors, clock skew reduction using variable clock drivers is presented. The second sensors embedded into functional circuits predict timing errors due to PVT variations and aging. By controlling circuit performance according to the sensor outputs, PVT worst-case design can be overcome and power dissipation can be reduced while satisfying performance requirements. Measurement results of a subthreshold adder on 65nm test chips show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding.