Archive for September, 2011

ICS Seminar: Prof. Sylvester

Posted on September 13, 2011

Prof. Dennis Sylvester
University of Michigan
Wednesday, Sep. 14th, 6:30pm, ENS 306

Enabling Millimeter-Scale Computing

Ubiquitous computing, particularly as it relates to miniaturized sensor nodes (e.g., smart dust), remains science fiction despite continued hype.  Why?  Simply put it is very challenging to create what are essentially invisible networked computers that can operate for months, years, or decades.  Despite Moore’s Law, this combination of form factor and lifetime constraints remain beyond the capabilities of modern integrated circuit design techniques.  This talk describes new integrated circuit building blocks to make this vision a reality.  Results from our own efforts in this space point to mm-scale systems as a new class of computing that will enable exciting new applications and promise to continue the information revolution well beyond PCs and handsets. 

ICS Seminar: Prof. Hashomito

Posted on September 13, 2011

Prof. Masanori Hashimoto
Osaka University, Osaka, Japan
Thursday, Sep. 1st, 3:00pm – 5:00pm

Adaptive Performance Compensation with On-Chip Variation Monitoring

This talk discusses adaptive performance control with two types of on-chip variation sensors. The first sensor gives estimates of die-to-die and spatially correlated variations that are decomposed into NMOS/PMOS threshold voltages and channel lengths. As a potential performance control with this type of sensors, clock skew reduction using variable clock drivers is presented. The second sensors embedded into functional circuits predict timing errors due to PVT variations and aging. By controlling circuit performance according to the sensor outputs, PVT worst-case design can be overcome and power dissipation can be reduced while satisfying performance requirements. Measurement results of a subthreshold adder on 65nm test chips show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding.