ICS Seminar: Prof. Massimo Alioto

Posted on March 20, 2010

Prof. Massimo Alioto
University of Siena / UC Berkeley
Monday, March 22, 5:00pm, ACES 2.402

Ultra-Low Power Logic Circuits: From Voltage-Mode to Current-Mode

In the last few years, subthreshold VLSI circuits have become very popular in ultra‐low power applications such as distributed sensing, wearable computing, biomedical devices, green electronics. These applications typically constrain the power budget to a few tens of μWs and the supply voltage to a few hundreds of mV. Operation at such low power/voltage poses new interesting problems and challenges, and at the same time offers new opportunities to develop emerging applications, as well as to stimulate and enable new technologies and markets. In this talk, opportunities and challenges in the ultra-low power domain are presented in the context of current nanometer technologies, and are put in perspective. On the one hand, a comparison with standard superthreshold VLSI design is presented to highlight the most critical challenges that we will face in the next years. On the other hand, the impact of next technology generations is analyzed from the point of view of energy consumption and robustness.

Process/voltage/temperature variability and leakage are analyzed in a consistent framework to show how they ultimately affect ultra-low power/voltage operation, and practical limits to the voltage scaling and energy minimization will be identified by resorting to simple models. Other than exploring the energy/voltage boundary of subthreshold VLSI circuits, circuit design methodologies to push down the voltage lower bound are presented. Guidelines on how to systematically build ultra-low power standard cell libraries are also discussed. For the first time, robustness and yield are considered as further dimensions in the design space. In particular, the speech aims at clarifying the important role (usually neglected) that the voltage lower bound plays in real VLSI circuits, and its relation with the optimal voltage that minimizes the energy consumption.

As an alternative approach to ultra‐low power computing, MOS Current Mode Logic (MCML) circuits are explored to understand limits and advantages over standard voltage-mode CMOS logic styles. Design issues arising in the ultra-low power realm with a power consumption in the order of pW-per-gate are discussed, and appropriate circuit techniques to allow reliable operation are ntroduced. Successful designs and state-of-the-art chips are presented to gain a clear understanding of the state-of-the-art, and which direction the research is moving to. Finally, open questions and aspects that require further investigation and new directions are highlighted.