Integrated Circuits and Systems Group

Dr. Jacob Kornerup
National Instruments, Austin
Wednesday, March 31, 5:00pm, ACES 2.402

Graphical System Design

Designers of today’s embedded systems are faced with numerous challenges in the process of going from idea to deliverable product. These challenges are growing as systems are becoming more complex and flexible and require more involvement throughout the design flow from domain experts.

A Graphical System Design Platform abstracts the growing complexity of designing embedded systems by offering intuitive graphical programming integrated with flexible, COTS hardware and optimized for domain experts needing a faster design process. The integrated hardware provides a customizable, robust design, prototyping and deployment platform which enables faster design iterations for rapidly changing designs, and integrates real-world I/O early in the design process for higher-quality results.

In this presentation I will give an overview of the challenges that many of our customers are facing when they are building embedded systems. I will then present National Instruments’ vision for Graphical System Design and illustrate some of the steps we are taking to realize this vision through a demo of a prototype system that combines graphical programming with system configuration and DSP algorithm development.

Mr. Nan Sun
Harvard University
Thursday, March 25, 10:00am, ENS 637

CMOS RF NMR Biosensor and Dual-Mode Pipelined ADC

I will present two of my recent works. First, I will present the work that showcases how silicon radio-frequency (RF) chips can be used not only for wireless RF applications, but also for biomolecular sensing aimed at low-cost disease screening. The main function of the RF chip is to manipulate and monitor the dynamics of protons in water via nuclear magnetic resonance (NMR). Target biological objects such as cancer marker proteins alter the proton dynamics, which is the basis for the biosensing. The high sensitivity of the RF chip made possible the construction of an entire NMR system around the RF chip in a 100-g platform, which is 1200 times lighter, yet 150 times more spin-mass sensitive than a state-of-the-art commercial benchtop NMR system. The system can become a useful addition in pursuing disease detection in a low-cost, hand-held platform.

Second, I will present the design of a high figure-of-merit (FOM) pipelined ADC, made possible by a new, dual-mode-based digital background calibration technique that altogether corrects errors caused by amplifier gain insufficiency and nonlinearity, and capacitor mismatches. The calibration enables the intentional use of low-gain single-stage op-amps to save power. It improves the measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 16 dB and 28 dB respectively, leading to the FOM of 155 fJ/conv-step.

Prof. Massimo Alioto
University of Siena / UC Berkeley
Monday, March 22, 5:00pm, ACES 2.402

Ultra-Low Power Logic Circuits: From Voltage-Mode to Current-Mode

In the last few years, subthreshold VLSI circuits have become very popular in ultra‐low power applications such as distributed sensing, wearable computing, biomedical devices, green electronics. These applications typically constrain the power budget to a few tens of μWs and the supply voltage to a few hundreds of mV. Operation at such low power/voltage poses new interesting problems and challenges, and at the same time offers new opportunities to develop emerging applications, as well as to stimulate and enable new technologies and markets. In this talk, opportunities and challenges in the ultra-low power domain are presented in the context of current nanometer technologies, and are put in perspective. On the one hand, a comparison with standard superthreshold VLSI design is presented to highlight the most critical challenges that we will face in the next years. On the other hand, the impact of next technology generations is analyzed from the point of view of energy consumption and robustness.

Process/voltage/temperature variability and leakage are analyzed in a consistent framework to show how they ultimately affect ultra-low power/voltage operation, and practical limits to the voltage scaling and energy minimization will be identified by resorting to simple models. Other than exploring the energy/voltage boundary of subthreshold VLSI circuits, circuit design methodologies to push down the voltage lower bound are presented. Guidelines on how to systematically build ultra-low power standard cell libraries are also discussed. For the first time, robustness and yield are considered as further dimensions in the design space. In particular, the speech aims at clarifying the important role (usually neglected) that the voltage lower bound plays in real VLSI circuits, and its relation with the optimal voltage that minimizes the energy consumption.

As an alternative approach to ultra‐low power computing, MOS Current Mode Logic (MCML) circuits are explored to understand limits and advantages over standard voltage-mode CMOS logic styles. Design issues arising in the ultra-low power realm with a power consumption in the order of pW-per-gate are discussed, and appropriate circuit techniques to allow reliable operation are ntroduced. Successful designs and state-of-the-art chips are presented to gain a clear understanding of the state-of-the-art, and which direction the research is moving to. Finally, open questions and aspects that require further investigation and new directions are highlighted.