Integrated Circuits and Systems Group

Aug. 30th, 6pm to 8pm

ACES Avaya Auditorium 2.302

Topic: Energy Limits in Current A/D Converter Architectures

Driven by ever-increasing application demands, the energy expended per A/D conversion has been reduced substantially over the last decade. This presentation will survey the most recent trends and will investigate energy limits as they apply to A/D converter architectures commonly employed in fine-line CMOS technology (Flash, Pipeline, SAR and Oversampling Converters). Through this analysis, opportunities for further improvements will be identified and discussed in detail, specifically emphasizing the impact of technology scaling.

Biography:

Boris Murmann is an Associate Professor in the Department of Electrical Engineering, Stanford, CA. He received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2003. From 1994 to 1997, he was with Neutron Mikrolektronik, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Dr. Murmann’s research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium in 2008 and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He currently serves as an Associate Editor of the IEEE Journal of Solid-State Circuits, the Data Converter Subcommittee Chair of the IEEE International Solid-State Circuits Conference (ISSCC) and as a program committee member of the European Solid-State Circuits Conference (ESSCIRC). He is a Distinguished Lecturer and elected AdCom member of the IEEE Solid-State Circuits Society.

Prof. Ian Galton
UCSD
4/2/2012, 11 am, NHB 1.720

Enhancement Techniques for Fractional-N PLL Frequency Synthesizers

Fractional-N phase-locked loops (PLLs) are widely used as RF local oscillators in wireless communication systems. Their performance is critical in such applications, so they are a subject of intensive research. This talk presents recently-developed techniques that mitigate several practical problems in fractional-N PLLs. Phase noise cancellation is presented as a means of relaxing the fundamental tradeoff between fractional-N PLL phase noise and loop bandwidth. A fast-settling adaptive calibration technique is presented that makes phase noise cancellation practical for the low reference frequencies commonly used in wireless communication systems. Various techniques that work in concert to suppress spurious tones are then presented. They include a new type of digital quantizer to replace the digital delta-sigma modulator used in conventional designs, a charge pump offset technique, and a sampled loop filter. A new type of fractional-N PLL with a digital loop filter to reduce circuit area and sensitivity to device leakage and low supply voltage is also presented. Throughout the talk, integrated circuit prototypes are presented in which the various techniques are shown to enable measured state-of-the-art performance.

Prof. Patrick Chiang
Oregon State University
Oct. 28th, 1:30pm, ACE 2.402

Wireless Sensors for the Non-Invasive Monitoring of Aging

Our goal is to develop a wearable sensor microsystem, capturing activity, indoor location, and critical vital signs, for assessing and monitoring independent living of the elderly. In 2009, more than 39.6 million Americans were over the age of 65 (5x more in China), and it is predicted that this number will more than double in the next 20-30 years. In-home monitoring technologies have a great potential to support independent living, by providing continuous critical health status information as well as early diagnosis of cognitive decline and subtle nutritional changes.

In this talk, I will describe the opportunities and challenges that lie in this interdisciplinary research area between sensing, computing, diagnosing, and ultimately, better health.  From a circuit designer’s standpoint, I will describe recent experimental prototypes that may enable a future world using non-invasive wearable sensors: a) indoor location tracking of precise movement/walking for the early detection of cognitive decline; b) near-threshold, robust DSP parallel processor for biomedical sensor signal processing; c) synchronized multi-node wireless body-area networks powered by RF energy harvesting.

Finally, I will discuss recent collaborations with clinicians, such as nutrition specialists (Linus Pauling Institute at OSU) and gerontologists (Oregon Health and Science medical school), attempting to take these captured sensed signals and translate them into healthy aging.