ICS Seminar: Prof. Susmita Sur-Kolay

Posted on October 10, 2012

Speaker: Professor Susmita Sur-Kolay, Indian Statistical Institute
Location: ACES 2.402
Time: Wednesday 10/10/2012, 2:30-3:30pm

Abstract: VLSI designs and hardware cores are reused in order to meet the design specifications on time, considering the numerous constraints imposed by nanometer technology. Electronic description of a VLSI design or a hardware core is an intellectual property (IP), and may be infringed upon either in the design house, or the fabrication facility, or at the time of its reuse in a system. This mandates incorporating techniques for intellectual property protection in the VLSI design flow. The IP of a VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs such as image, text, because in addition to its physical and structural description, it also has a behavioral specification which should remain unaltered by any IP protection technique. IPs at the design level are editable and hence more flexible for reuse yet more vulnerable to misappropriation. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security. This talk aims at presenting the major concerns in IP security and the challenges to implement the countermeasures and retain their effectiveness in the entire life cycle.

Brief bio:
Susmita Sur-Kolay received the B.Tech degree from Indian Institute of Technology Kharagpur and the Ph.D.degree from Jadavpur University India. She was a Research Assistant at Massachusetts Institute of Technology, post-doctoral fellow at University of Nebraska-Lincoln and Visiting Faculty at Intel Corp., USA. She is presently a Professor in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India.

Her research contributions are in the areas of algorithmic CAD for VLSI physical design, fault modeling and test-ing, IP protection of VLSI design, synthesis of quantum computers, graph algorithms. She has authored several technical papers in international journals and refereed conference proceedings and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She was the Technical Program Co-Chair of VLSI Design Conference 2005, VDAT 2007, ISVLSI 2011, and has served on the program committees of several international conferences. She has also been on the editorial board of Proc. of IEE CDT, and an Associate Editor of the IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Member of ACM, IET and VLSI Society of India. Two papers co-authored by her won best paper awards at two international conferences. Among many other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur and IBM Faculty Award.

ICS Seminar: Wolfgang Kunz

Posted on October 9, 2012

System- versus RT-Level Verification of Systems-on-Chip by Compositional Path Predicate Abstraction

Speakers: Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Dept. of Electrical & Computer Engineering
Technische Universität Kaiserslautern

ACES 2.402
Wednesday, October 10
4:30 – 5:30 p.m.

Abstract

We propose a new methodology to create a formal relationship between a time-abstract system-level description of a System-on-Chip (SoC) and its Register-Transfer Level (RTL) implementation. This formal relationship, called path predicate abstraction, is a weak form of a bisimulation and can be obtained by standard property checking techniques when applied in a systematic way. The proposed concepts can be used for bottom-up system verification as well as for top-down design refinements.

Since our methodology considers time-abstract system models individually for each SoC module there is the challenge to deal with the concurrency between the individual RTL components. We propose a compositional scheme describing the communication between SoC modules independently of their individual processing speed. The composed abstract system is modeled by an asynchronous composition and can be verified using the SPIN model checker.

We demonstrate the practical feasibility of our approach by a comprehensive case study based on Infineon’s FPI Bus. We show that SPIN in combination with our methodology is able to prove global system properties for the RTL implementation consisting of several concurrent SoC modules and containing thousands of state variables.

 

ICS Seminar: Dr. Ruchir Puri, IBM Fellow

Posted on September 27, 2012

Wednesday, October 3, 2012

2:00 PM  (1:30pm Reception)
NHB 1.720
(NHB – Norman Hackerman Building is diagonally across the ACES Building at the intersection of 24th and Speedway)

Opportunities and Challenges for High Performance Microprocessor Designs and Design Automation

With end of an era of classical technology scaling and exponential frequency increases, high end microprocessor designs and design automation methodologies are at an inflection point. With power and current demands reaching breaking points, and significant challenges in application software stack, we are also reaching diminishing returns from simply adding more cores. In design methodologies for high end microprocessors, although chip physical design efficiency has seen tremendous improvements, strong indications are emerging for maturing of those gains as well. In order to continue the cost-performance scaling in systems in light of these maturing trends, we must innovate up the design stack, moving focus from technology and physical design implementation to new IP and methodologies at Logic, architecture, and at the boundary of hardware and software, solving key bottlenecks through application acceleration. This new era of innovation, which moves the focus up the design stack presents new challenges and opportunities to the design and design automation communities. This talk will motivate these trends and focus on challenges for high performance microprocessor design and design automation in the years to come.

 

Speaker Biography
Ruchir Puri is an IBM Fellow at Thomas J Watson Research Center, Yorktown Hts, NY where his efforts have focused on high performance design and methodology solutions for all of IBM’s enterprise server and system chip designs. Most recently, he lead the design methodology innovations for IBM’s latest Power7 and zEnterprise microprocessors and is currently leading design methodology research efforts on future processors.   Ruchir has received numerous IBM awards including the highest technical honor – IBM Fellow, which was awarded for his transformational role in microprocessor design methodology. In addition, he has received “Best of IBM” awards in both 2011 and 2012 and IBM Corporate Award from IBM’s CEO, and several IBM Outstanding Technical Achievement awards. Dr. Puri is a Fellow of the IEEE, a member of IBM Academy of Technology and IBM Master Inventor, an ACM Distinguished Speaker and IEEE Distinguished Lecturer. He is recipient of SRC outstanding mentor award and has been an adjunct professor at Dept. of Electrical Engineering, Columbia University, NY and was also honored with John Von-Neumann Chair at Institute of Discrete Mathematics at Bonn University, Germany.  

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