Integrated Circuits and Systems Group

Dr. Ashish Singh
Department of Electrical and Computer Engineering, UT Austin
Wednesday, March 3, 5:00pm, ACES 2.402

Application of Statistical Optimization for Process and Defect Tolerant Nanometer Scale Circuit Design

The technology scaling is helping to achieve higher integration density and frequency in each technology generation. However, at the same time there is an increasing unpredictability in the physical properties of semiconductor devices because of lack of manufacturing control. The future nanodevices are predicted to have even higher variability and defects due to manufacturing limitations. This necessitates a tighter integration of process and design flows. Due to statistical nature of the process variation, we must deal with statistical design methodology since developing such a methodology can reduce the impact of yield loss incurred due to high variability.

A major challenge is to develop efficient parametric yield optimization algorithms at different levels of abstraction in the design flow. In order to address this problem, my work has mainly focused on developing efficient tractable approximations that can be employed to overcome the high computational complexity of the statistical problem that are encountered during logic synthesis, post-synthesis optimization, circuit timing prediction and robust memory design.

In this talk, I will give a brief overview of my work in these areas. I will cover in details, the methods for yield constrained power optimization using joint design time and post-silicon tuning methods for logic and SRAM. I will also discuss the challenges associated with defect tolerance in future nanotechnologies and in particular a defect tolerant CMOS-CNT (Carbon Nano Tube) architecture using novel coding of Boolean functions.

Prof. Luca Carloni
Department of Computer Science, Columbia University
Tuesday, February 23, 3:30pm, ACES 2.302

System-Level Design of Embedded Platform Architectures

The heterogeneous and distributed nature of many emerging classes of
embedded applications adds a new level of design complexity requiring the
deployment of tightly-interactive, concurrent processes on networked
platform architectures. While the design of a single component is
important, the critical challenges in the realization of a system-on-chip or a
distributed embedded system lie in the integration of the components. In
addressing these challenges we sustain that communication plays an
increasingly central role both at design time and run time. We present a
communication-based system-level design methodology that simplifies the
integrated design and validation of embedded platform architectures while
enabling important properties like modularity, scalability, flexibility, and
reusability. In particular, we argue how effective design space exploration
can be achieved through the decoupling of the design of the computational
elements and the synthesis of the communication infrastructure. For the
latter we present recent results on the design and optimization of
networks-on-chip.

Professor Jim Plusquellic
University of New Mexico
Thursday, November 5, 5pm, ACES 2.402

Design for Manufacturability: Embeddable Test Structures for Measuring Process Variations and Assessing DFM Practices

 Techniques to improve Design for Manufacturability (DFM) has been around for a long time, e.g. a technology’s design rules represent an early form of DFM. However, when technology was scaled to 180 nm — a feature size smaller than the wavelength of the light source used in photolithography (193 nm) — sub-resolution printability issues became a major concern. Reticle enhancement techniques, such as optical proximity correction, phase shift masking and off-axis illumination, were introduced to improve printability and have enjoyed a great deal of success.However, these techniques have become increasingly less effective as technologies scaled to and below 45 nm, resulting in higher levels of both random and systematic process variations and in the more frequent occurrence of systematic defects. In my presentation, I will describe structured “circuit context”-oriented techniques that are designed to measure the impact of random and systematic process variations, such as those that introduce variations in metal resistance and leakage, and will present data collected from ICs fabricated in IBM’s 65 nm SOI process. The proposed test structures and techniques are designed to provide regional, layout-oriented information about these variations across the 3-D topology of the IC. I will also describe an embeddable test structure for measuring the delay variations introduced by SOI history effect. Time permitting, I will discuss our proposed test structures and infrastructures that are designed to assess the impact of various DFM practices on functional and parametric yield.