Books by ICSG Faculty

Adnan Aziz, Amit Prakash, Algorithms For Interviews, Createspace, 2010.

 

Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, and Gunar Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, 2009.

 

Ranjit Gharpurey, Peter Kinget (editors), Ultra Wideband: Circuits, Transceivers and Systems, Springer, 2008.

 

Michael Orshansky, Sani Nassif, Duane Boning, Design for Manufacturability and Statistical Design: A Constructive Approach, Springer, 2008.

 

Jun Yuan , Carl Pixley, Adnan Aziz, Constraint-Based Verification, Springer, 2007.

 

Edoardo Charbon, Ranjit Gharpurey, Paolo Miliozzi, and Robert G. Meyer, Substrate Noise: Analysis and Optimization for IC Design, Springer, 2007.

 

Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2007.

 

Achim Rettberg, Achim Rettberg, Mauro Zanella, Rainer Domer, Andreas Gerstlauer, Franz Rammig  (editors), Embedded System Design: Topics, Techniques and Trends, Springer, 2007.

 

Andreas Gerstlauer, Rainer Dömer, Junyu Peng, and Daniel D. Gajski, System Design: A Practical Guide with SpecC, Kluwer Academic Publishers, 2001.

 

Daniel D. Gajski, Jianwen Zhu, Rainer Domer, and Andreas Gerstlauer, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000.

 

 

Selected Conference and Journal Papers

Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal, “Characterization of Sequential Cells for Constraint Sensitivities,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 74-79, March 2009.

 

Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, “Functionally Valid Gate-Level Peak Power Estimation for Processors,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 753-758, March 2009.

 

Stephen Bijansky, Sae Kyu Lee, Adnan Aziz, “TuneLogic: Post-Silicon Tuning of Dual-Vdd Designs,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 394-400, March 2009.

 

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan, “On Efficient Generation of Instruction Sequences to Test for Delay Defects in a Processor,” Proc. ACM Great Lakes Symposium on VLSI, pp. 279-284, May 2008.

 

Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham, “Analytical Model for the Impact of Multiple Input Switching Noise on Timing,” Proc. Asia South Pacific Design Automation Conference, pp. 514-517, January 2008.

 

Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham, “Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL,” Proc. VLSI Design, pp. 77-82, January 2009.

 

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan, “On Efficient Generation of Instruction Sequences to Test for Delay Defects in a Processor,” Proc. ACM Great Lakes Symposium on VLSI, pp. 279-284, May 2008.

 

Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham, “Analytical Model for the Impact of Multiple Input Switching Noise on Timing,” Proc. Asia South Pacific Design Automation Conference, pp. 514-517, January 2008.

 

Stephen Bijansky, Adnan Aziz, “TuneFPGA: Post-Silicon Tuning of Dual-Vdd FPGAs,” Proc. Design Automation Conference, pp. 796-799, June 2008.

 

Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham, “Adaptive SRAM Memory for Low Power and High Yield,” Proc. International Conference on Computer Design, pp. 176-181, October 2008.

 

Gunar Schirner, Andreas Gerstlauer, Rainer Dömer, “Automatic Generation of Hardware Dependent Software for MPSoCs from Abstract System Specifications,” Proc. Asia South Pacific Design Automation Conference, pp. 271-276, January 2008.

 

Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, A. Nakamura, Dai Araki, Y. Nishihara, “Specify-Explore-Refine (SER): From Specification to Implementation,” Proc. Design Automation Conference, pp. 586-591, January 2008.

 

Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, “An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors,” Proc. IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 4,

pp. 466-475, January 2008.

 

Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham, “Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors,” Proc. IEEE VLSI Test Symposium, pp. 203-208, April-May 2008.

 

Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram, “Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method,” Proc. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, pp. 1595-1606, January 2008.

 

Lawrence H. Ragan, Arjang Hassibi, Theodore S. Rappaport, Craig L. Christianson, “Novel On-Chip Antenna Structures and Frequency Selective Surface (FSS) Approaches for Millimeter Wave Devices,” Proc. IEEE Vehicular Technology Conference, pp. 2051-2055, September-October 2007.

 

A. Hassibi, H. Vikalo, J. L. Riechmann and B. Hassibi, “Real-time DNA Microarray Analysis,” Nucleic Acids Research, doi:10.1093/nar/gkp675, pp. 1-12, August 2009.

 

G. Li, Y. Tousi, A. Hassibi, and E. Afshari, “Delay-line Based Analog-to-Digital Conversion,” Proc. IEEE Transactions On Circuits And Systems—II: Express Briefs, vol. 56, no. 6, June 2009.

 

A. Hassibi, Aydin Babakhani and Ali Hajimiri, “A Spectral-Scanning Nuclear Magnetic Resonance Imaging (MRI) Transceiver,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44  iss. 6, pp. 44-6, June 2009.

 

S. Banerjee, K. B. Agarwal, J. A. Culp, P. Elakkumanan, L. W. Liebmann, and M. Orshansky, “Compensating Non-Optical Effects Using Electrically Driven Optical Proximity Correction,” Proc. Society of Photo-Optical Instrumentation Engineers, vol. 7275, pp. 72750E-72750E-10, 2009.

 

A. K. Singh, K. He, C. Caramanis, and M. Orshansky, “Mitigation of Intra-Array SRAM Variability using Adaptive Voltage Architecture,” Proc. International Conference on Computer Aided Design, November 2009.

 

Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky, “Electrically Driven Optical Proximity Correction Based on Linear Programming,” Proc. International Conference on Computer Aided Design, pp. 473-479, November 2008.

 

M. Orshansky and W. S. Wang, “Statistical Analysis of Circuit Timing Using Majorization,” Communications of the ACM (CACM), vol. 52, no. 8, August 2009.

 

Bin Zhang, Michael Orshansky, “Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 774-779, March 2008.

 

Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet Roychowdhury, Douglas L. Jones, Jan M. Rabaey, “The Search for Alternative Computational Paradigms,” IEEE Design & Test of Computers, vol. 25, no. 4, pp. 334-343, 2008.

 

Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan, “BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability,” ACM Transactions on Design Automation of Electronic Systems, vol. 14, no. 2, March 2009.

 

David Z. Pan, Minsik Cho, “Synergistic Physical Synthesis for Manufacturability and Variability in 45nm Designs and Beyond,” Proc. Asia South Pacific Design Automation Conference, pp. 220-225, January 2008.

 

Anand Rajaram, David Z. Pan, “MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks,” Proc. Asia South Pacific Design Automation Conference, pp. 250-257, January 2008.

 

Tao Luo, David Z. Pan, “DPlace2.0: A Stable and Efficient Analytical Placement Based on Diffusion,” Proc. Asia South Pacific Design Automation Conference, pp. 346-351, January 2008.

 

Tao Luo, David Newmark, David Z. Pan, “Total Power Optimization Combining Placement, Sizing and Multi-Vt through Slack Distribution Management,” Proc. Asia South Pacific Design Automation Conference, pp. 352-357, January 2008.

 

Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan, “ELIAD: Efficient Lithography Aware Detailed Router with Compact Post-OPC Printability Prediction,” Proc. Design Automation Conference, pp. 504-509, June 2008.

 

Joon-Sung Yang, Nur A. Touba, “Enhancing Silicon Debug via Periodic Monitoring,” Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 125-133, October 2008.

 

Joon-Sung Yang, Nur A. Touba. “Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture,” Proc. IEEE VLSI Test Symposium, pp. 345-351, April-May 2008.

 

Ritesh Garg, Richard Putman, Nur A. Touba, “Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation,” Proc. IEEE VLSI Test Symposium, pp. 35-42, April-May 2008.

 

Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba, Proc. IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, September 2007.

 

Tongyu Song, Shouli Yan, “A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter,” Proc. IEEE International Symposium on Circuits and Systems, pp. 477-480, May 2007.

 

Gonggui Xu, Shouli Yan, “An Improved Frequency and Phase Synthesis Architecture,” Proc. International Symposium on Circuits and Systems, pp. 4171-4174, May 2006.