Archive for October, 2012

ICS Seminar: Prof. Michael Perrott

Posted on October 10, 2012

Thursday, October 11, 2012

6:00-8:00pm
ACE 2.402

First Talk Abstract:

VCO-based quantizers take advantage of the steadily increasing speed of modern CMOS processes by quantizing time rather than amplitude. Their implementation leads to highly digital architectures that benefit directly from Moore’s law, and offer intriguing benefits such as inherent shaping of their quantization noise. In this talk, we examine their potential for achieving high resolution analog-to-digital conversion (ADC), and identify key shortcomings such as nonlinearity of the voltage-to-frequency characteristic and its impact on SNDR. Circuit techniques are then presented to overcome such shortcomings, along with recent results verifying their effectiveness. In particular, we show that using phase rather than frequency within a continuous-time Sigma-Delta ADC topology enables 78dB SNDR performance within 20MHz bandwidth with a power efficiency of 330 fJ/conversion step. Finally, we conclude by generalizing the VCO-based quantizer as an efficient combination of a voltage-to-time converter and a time-to-digital converter, and discuss its advantages compared to other recent approaches which combine these components.

Second Talk Abstract:

This talk presents a MEMS-based programmable oscillator which achieves better than +/-0.5ppm frequency stability from -40 degrees C to 85 degrees C and less than 1ps (rms) integrated phase noise (12kHz to 20MHz). We focus on the key component of this system, which is a thermistor-based temperature-to-digital converter (TDC) that enables accurate and low noise compensation of temperature-induced variation of the MEMS resonant frequency. The TDC utilizes several circuit techniques including a high resolution, tunable reference resistor based on a switched capacitor network and fractional-N frequency division, a switched resistor measurement approach which allows a pulsed bias technique for reduced noise, and a VCO-based quantizer for digitization of the temperature signal. To verify the effectiveness of these techniques, measured performance of a 180nm CMOS IC with co-packaged MEMS die is presented which demonstrates 0.1mK (rms) resolution for the TDC within a 5Hz bandwidth and power consumption of 3.97mA with 3.3V supply.

Biography:

Michael H. Perrott received the B.S. degree in Electrical Engineering from New Mexico State University, Las Cruces, NM in 1988, and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from Massachusetts Institute of Technology in 1992 and 1997, respectively. From 1997 to 1998, he worked at Hewlett-Packard Laboratories in Palo Alto, CA, on high speed circuit techniques for Sigma-Delta synthesizers. In 1999, he was a visiting Assistant Professor at the Hong Kong University of Science and Technology. From 1999 to 2001, he worked at Silicon Laboratories in Austin, TX, and developed circuit and signal processing techniques to achieve high performance clock and data recovery circuits. He was an Assistant and then Associate Professor in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology from 2001 to 2008. He was with SiTime Corporation from 2008 to 2010, where he developed key technology for MEMS-based oscillators. He is currently a professor at Masdar Institute in Abu Dhabi, where he is focusing on low power, mixed-signal circuits for health and fitness and other applications.

ICS Seminar: Prof. Susmita Sur-Kolay

Posted on October 10, 2012

Speaker: Professor Susmita Sur-Kolay, Indian Statistical Institute
Location: ACES 2.402
Time: Wednesday 10/10/2012, 2:30-3:30pm

Abstract: VLSI designs and hardware cores are reused in order to meet the design specifications on time, considering the numerous constraints imposed by nanometer technology. Electronic description of a VLSI design or a hardware core is an intellectual property (IP), and may be infringed upon either in the design house, or the fabrication facility, or at the time of its reuse in a system. This mandates incorporating techniques for intellectual property protection in the VLSI design flow. The IP of a VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs such as image, text, because in addition to its physical and structural description, it also has a behavioral specification which should remain unaltered by any IP protection technique. IPs at the design level are editable and hence more flexible for reuse yet more vulnerable to misappropriation. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security. This talk aims at presenting the major concerns in IP security and the challenges to implement the countermeasures and retain their effectiveness in the entire life cycle.

Brief bio:
Susmita Sur-Kolay received the B.Tech degree from Indian Institute of Technology Kharagpur and the Ph.D.degree from Jadavpur University India. She was a Research Assistant at Massachusetts Institute of Technology, post-doctoral fellow at University of Nebraska-Lincoln and Visiting Faculty at Intel Corp., USA. She is presently a Professor in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India.

Her research contributions are in the areas of algorithmic CAD for VLSI physical design, fault modeling and test-ing, IP protection of VLSI design, synthesis of quantum computers, graph algorithms. She has authored several technical papers in international journals and refereed conference proceedings and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She was the Technical Program Co-Chair of VLSI Design Conference 2005, VDAT 2007, ISVLSI 2011, and has served on the program committees of several international conferences. She has also been on the editorial board of Proc. of IEE CDT, and an Associate Editor of the IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Member of ACM, IET and VLSI Society of India. Two papers co-authored by her won best paper awards at two international conferences. Among many other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur and IBM Faculty Award.

ICS Seminar: Wolfgang Kunz

Posted on October 9, 2012

System- versus RT-Level Verification of Systems-on-Chip by Compositional Path Predicate Abstraction

Speakers: Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Dept. of Electrical & Computer Engineering
Technische Universität Kaiserslautern

ACES 2.402
Wednesday, October 10
4:30 – 5:30 p.m.

Abstract

We propose a new methodology to create a formal relationship between a time-abstract system-level description of a System-on-Chip (SoC) and its Register-Transfer Level (RTL) implementation. This formal relationship, called path predicate abstraction, is a weak form of a bisimulation and can be obtained by standard property checking techniques when applied in a systematic way. The proposed concepts can be used for bottom-up system verification as well as for top-down design refinements.

Since our methodology considers time-abstract system models individually for each SoC module there is the challenge to deal with the concurrency between the individual RTL components. We propose a compositional scheme describing the communication between SoC modules independently of their individual processing speed. The composed abstract system is modeled by an asynchronous composition and can be verified using the SPIN model checker.

We demonstrate the practical feasibility of our approach by a comprehensive case study based on Infineon’s FPI Bus. We show that SPIN in combination with our methodology is able to prove global system properties for the RTL implementation consisting of several concurrent SoC modules and containing thousands of state variables.