ICS Seminar: Professor Jim Plusquellic
Professor Jim Plusquellic
University of New Mexico
Thursday, November 5, 5pm, ACES 2.402
Design for Manufacturability: Embeddable Test Structures for Measuring Process Variations and Assessing DFM Practices
Techniques to improve Design for Manufacturability (DFM) has been around for a long time, e.g. a technology’s design rules represent an early form of DFM. However, when technology was scaled to 180 nm — a feature size smaller than the wavelength of the light source used in photolithography (193 nm) — sub-resolution printability issues became a major concern. Reticle enhancement techniques, such as optical proximity correction, phase shift masking and off-axis illumination, were introduced to improve printability and have enjoyed a great deal of success.However, these techniques have become increasingly less effective as technologies scaled to and below 45 nm, resulting in higher levels of both random and systematic process variations and in the more frequent occurrence of systematic defects. In my presentation, I will describe structured “circuit context”-oriented techniques that are designed to measure the impact of random and systematic process variations, such as those that introduce variations in metal resistance and leakage, and will present data collected from ICs fabricated in IBM’s 65 nm SOI process. The proposed test structures and techniques are designed to provide regional, layout-oriented information about these variations across the 3-D topology of the IC. I will also describe an embeddable test structure for measuring the delay variations introduced by SOI history effect. Time permitting, I will discuss our proposed test structures and infrastructures that are designed to assess the impact of various DFM practices on functional and parametric yield.