Integrated Circuits and Systems Group

ICSG carries out research that spans all major areas of design and design methodology for digital, analog, mixed-signal, and RF CMOS ICs.

Date: Mon, Oct. 19, 2015

Time: 6-8pm

Place: POB 2.402

Talk title: MICROPOWER INCREMENTAL A/D CONVERTERS

Talk abstract: Integrated sensor interfaces need high-resolution and power-efficient data converters. In some applications, a single A/D converter has to be multiplexed between many sensors. Often, the optimum choice for the ADC architecture is the incremental data converter (IDC). An IDC is a memory-less (Nyquist-rate) ADC, which uses an embedded delta-sigma (ΔΣ) ADC and a digital postfilter to achieve very high accuracy (say, 22 ENOB) through noise shaping. As in a ΔΣ ADC, the accuracy can be enhanced by cascading several ADC stages to achieve noise cancellation. The resulting extended counting ADC (EDC) may share the hardware between several stages.

In this seminar, a tutorial introduction will be given which explains the peculiar features of IDCs and EDCs, as well as the relative merits and limitations of IDCs vs. conventional Nyquist-rate ADCs and ΔΣ ADCs. After that, our recent research results on the design of micro-power IDCs and EDCs will be discussed, and illustrated with implemented data converters.

Speaker bio: Gabor C. Temes is a Life Fellow of IEEE. He published over 600 research papers, and wrote or coauthored five books on circuit design, translated into Chinese, Japanese, Russian and other languages. He holds 15 patents on novel circuits and devices. He served as Editor of IEEE TCAS-I. He received the CAS Darlington Award, and the CAS Education as well as Technical Achievement Awards. He won the 1998 IEEE Graduate Teaching Award, the 2006 IEEE Gustav Robert Kirchhoff Award, and the 2009 CAS Mac Van Valkenburg Award. He is a member of the U.S. National Academy of Engineering.

Date: Thursday, September 24, 2015

Time: 10:00 – 11:00 AM

Place: POB 2.402

Talk title: logic debugging by replacing internal gates with new functions

Talk abstract: Firs is a general QBF (Quantified Boolean Formula)-based formulation and its SAT-based solver which can be applied to partial logic synthesis.  It can deal with problems including logic debugging, test pattern generation for multiple functional faults and logic optimization. Then we show its application and extension for logic debugging by replacing internal gates with new appropriate functions.  We describe experiences on debugging industrial circuits, and based on them define different problems: replacing only functions of internal gates (no change in circuit topology), replacing internal gates with new functions of primary inputs, and replacing internal gates with new functions of internal signals.  The last one is the most general approach for logic debugging, but needs new formulations.  A new search method for good internal signals as inputs to the replacing functions, which is based on QBF formulation, is presented. This method is quite different from the previous ones in the sense that it searches for not only appropriate functions which replace the target gates, but also their inputs out of all internal signals.

Biography:

Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT-based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs having more than several million gates. The developed tool has been used in production internally at Fujitsu and externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has been involved in a Japanese governmental research project for dependable system designs and has developed a formal verifier for C programs that could be used for both hardware and embedded software designs. The tool is now under evaluation jointly with industry under governmental support. He has authored and co-authored 10 books, and has more than 200 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of web-based programs and embedded programs.

Title: Overview of the Methods for Design of Application Specific Integrated Circuits (ASICs) Explored at the IHP Institute at Frankfurt (Oder), Germany

Research institute IHP – Innovation for High Performance Microelectronics performs the cutting edge research activities in the area of high frequency integrated circuits. Based on its internal BiCMOS technology with high performance bipolar transistors (fmax=500 GHz) the main topic is the development of wireless communication systems for telecommunications, aerospace, medicine, and automation. In the latest years, following the strategy More than Moore, several additional research directions have been established including graphene transistor development, microfluidics, RF MEMS, integrated BiMCOS-Silicon Photonics process, Terahertz electronics, high performance broadband networks, ultra-low power sensor networks etc.

In this talk an overview of the various research activities at IHP will be provided. The main focus will be on the activities of ASIC design and test method group at IHP. The focus of this group are the innovative design methods for low-power, low-noise, and fault tolerant ASICs. One of the major topics is asynchronous and globally asynchronous locally synchronous (GALS) circuit design. This talk will disclose low-EMI features of GALS technique, which are extremely important for complex implementations in scaled technologies and mixed SoC designs. The achieved results measured on complex CMOS chip named Moonrake in the scaled 40 nm CMOS process showed that EMI reduction of up to 26 dB could be achieved using GALS technology. With respect to fault tolerant design techniques, the main focus was on adaptive multi-core processor development for space. With the active hardware support several modes of operation of the multi-core system have been enabled, including fault tolerant and lifetime extension mode. The demonstrator chip has been implemented, integrating 8-core system, and recently successfully tested.

Resume:
Milos Krstic received his M.Sc. degree in Electrical Engineering at Faculty of Electronic Eng. Nis, Serbia in 2001, and his Dr.-Ing. degree from the Brandenburg University of Technology, Cottbus, Germany in 2006. Since 2001 he has been with IHP Microelectronics, Frankfurt (Oder), Germany, in the Wireless Communication Systems Department. For the last few years, his work was mainly focused on digital design techniques for wireless applications, fault tolerant ASIC design, and globally-asynchronous locally-synchronous (GALS) methodologies for digital systems integration. Since 2010 he is leading the group for Design & Test methodology that includes 15 researchers and test engineers. He was coordinating EU project GALAXY on GALS methodology for system integration, and now leads various projects in the area of GALS design, switching noise reduction techniques, radhard and fault tolerant design for space applications. His academic and professional work was followed with more than 90 journal and conference papers and 11 submitted patent applications (7 registered patents).