Welcome to the Integrated Circuits and Systems Group (ICSG) at the University of Texas at Austin

ICSG carries out research that spans all major areas of design and design methodology for digital, analog, mixed-signal, and RF CMOS ICs.

ICS Seminar: Dr. Milos Krstic, POB 2.402, May 7, 4-5pm

Posted on April 14, 2015

Title: Overview of the Methods for Design of Application Specific Integrated Circuits (ASICs) Explored at the IHP Institute at Frankfurt (Oder), Germany

Research institute IHP – Innovation for High Performance Microelectronics performs the cutting edge research activities in the area of high frequency integrated circuits. Based on its internal BiCMOS technology with high performance bipolar transistors (fmax=500 GHz) the main topic is the development of wireless communication systems for telecommunications, aerospace, medicine, and automation. In the latest years, following the strategy More than Moore, several additional research directions have been established including graphene transistor development, microfluidics, RF MEMS, integrated BiMCOS-Silicon Photonics process, Terahertz electronics, high performance broadband networks, ultra-low power sensor networks etc.

In this talk an overview of the various research activities at IHP will be provided. The main focus will be on the activities of ASIC design and test method group at IHP. The focus of this group are the innovative design methods for low-power, low-noise, and fault tolerant ASICs. One of the major topics is asynchronous and globally asynchronous locally synchronous (GALS) circuit design. This talk will disclose low-EMI features of GALS technique, which are extremely important for complex implementations in scaled technologies and mixed SoC designs. The achieved results measured on complex CMOS chip named Moonrake in the scaled 40 nm CMOS process showed that EMI reduction of up to 26 dB could be achieved using GALS technology. With respect to fault tolerant design techniques, the main focus was on adaptive multi-core processor development for space. With the active hardware support several modes of operation of the multi-core system have been enabled, including fault tolerant and lifetime extension mode. The demonstrator chip has been implemented, integrating 8-core system, and recently successfully tested.

Resume:
Milos Krstic received his M.Sc. degree in Electrical Engineering at Faculty of Electronic Eng. Nis, Serbia in 2001, and his Dr.-Ing. degree from the Brandenburg University of Technology, Cottbus, Germany in 2006. Since 2001 he has been with IHP Microelectronics, Frankfurt (Oder), Germany, in the Wireless Communication Systems Department. For the last few years, his work was mainly focused on digital design techniques for wireless applications, fault tolerant ASIC design, and globally-asynchronous locally-synchronous (GALS) methodologies for digital systems integration. Since 2010 he is leading the group for Design & Test methodology that includes 15 researchers and test engineers. He was coordinating EU project GALAXY on GALS methodology for system integration, and now leads various projects in the area of GALS design, switching noise reduction techniques, radhard and fault tolerant design for space applications. His academic and professional work was followed with more than 90 journal and conference papers and 11 submitted patent applications (7 registered patents).

ICS seminar: Prof. Jan Van der Spiegel of University of Pennsylvania

Posted on October 6, 2014

Topic: Bio-inspired Polarization Imagers – Making the invisible visible

Location and date: POB (ACES) 2.402, Oct. 21, 6pm

Biology provides us with fascinating examples of intelligent, low power, and highly efficient sensory systems. With the advances in CMOS technology, it has become feasible to build microelectronic systems that mimic some of the key features found in biology. This talk will focus on CMOS vision sensors for polarization imaging. We will review briefly the concepts of polarization and how it is used by various species in nature to enhance their vision or to aid with navigation and communication. Inspired by the biology we have explored polarization for a variety of applications to detect features that are hard to see or even invisible to the human eye. More recent results from the literature including the use of polarization imaging for disease detection will be reviewed. Motivated by the potential advantages of polarization imaging, we have developed a CMOS imager that combines the pixel array with micropolarizers and on-chip processing. Details of the design and polarizer optimization will be described.

Biography: Jan Van der Spiegel is a Professor of the Electrical and Systems Engineering Department, the Associate Dean for Education and the Director of the Center for Sensor Technologies at the University of Pennsylvania. Dr. Van der Spiegel received his Masters degree in Electro-Mechanical Engineering and his Ph.D. degree in Electrical Engineering from the University of Leuven, Belgium. His primary research interests are in mixed-mode VLSI design, CMOS vision sensors for polarization imaging, biologically based image sensors and brain-machine interfaces. He is the author of over 160 journal and conference papers and holds 4 patents. He is a fellow of the IEEE, the recipient of the IEEE Major Educational Innovation Award, the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He has served on several IEEE program committees and was the technical program chair of the 2007 International Solid-State Circuit Conference (ISSCC 2007). He is a member of the IEEE Solid-State Circuits Society AdCom, has been the SSCS chapters Chairs coordinator, associate editor of the Transaction of BioCAS, and is the former Editor of Sensors and Actuators A for North and South America. He is currently the president elect of the IEEE SSCS.

ICS seminar: Prof. Seng-Pan U from University of Macau

Posted on October 6, 2014

Location and date: POB (ACES) 2.402, Oct. 20th, 12pm

Topic: Energy Efficient SAR-Type ADC Design – Trends and Techniques

The evolving broadband wireless communication increasingly drives fast development on high-performance consumer portable smart and green gadgets with longer battery life, which leads to growing demands on high-speed ADCs with higher energy efficiency. SAR-type ADCs which take advantages of CMOS technology downscaling for their “highly digital” implementation have been dominating large segments of high-speed and energy efficient ADCs with efficiencies down to fJ/conversion step at 100MHz+ sampling rate. This talk provides firstly an overview of the state-of-the-art SAR-Type high energy-efficient ADCs, and then present the trends of the ADCs through the energy, speed and noise Analysis for various architectures including SAR & Binary-Search, Multi-bit SAR, Flash SAR and Pipeline SAR, Time-interleaved and etc. Practical design examples and techniques will be also addressed.

Biography: Seng-Pan U (Ben) received joint Ph.D. degree from the University of Macau (UM) and the Instituto Superior Técnico (IST), Portugal in 2002. He is currently Professor and Deputy Director of State-Key Lab. of Analog & Mixed-Signal VLSI of UM. He is the co-founder of Chipidea Microelectronics (Macau), Ltd. (currently Synopsys Macau Ltd) for analog & mixed-signal IP development and is also Senior Analog Design Manager and Site General Manager. He published 130+ papers and 4 books in Springer and China Science Press in the area of VHF SC filters, Analog Baseband for Multi-standard wireless transceivers and Very High-Speed TI ADCs, and he co-holds 10+ US patents. As the founding chair, he received the 2012 IEEE SSCS Outstanding Chapter Award. He received both the 2012 Macau Science & Technology (S&T) Invention and Progress Award. Both at the 1st time from Macau, he received the S&T Innovation Award of Ho Leung Ho Lee Foundation in 2010, and also The State S&T Progress Award in 2011. In recognition of his contribution in high-technology research & industrial development in Macau, he was awarded by Macau SAR government the Honorary Title of Value in 2010. He was also awarded as the “Scientific Chinese of the Year 2012”. He is also advisor for 20+ student award recipients, incl. ISSCC Silk-Road Award & A-SSCC Student Design Contest for data converter papers. He is currently IEEE SSCS Distinguished Lecturer (2014-2015), TPC of ISSCC, A-SSCC, VLSI-DAT, RFIT and Editorial Board member of Springer journal AICSP.

 

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