Integrated Circuits and Systems Group

ICSG carries out research that spans all major areas of design and design methodology for digital, analog, mixed-signal, and RF CMOS ICs.

Professor Jim Plusquellic
University of New Mexico
Thursday, November 5, 5pm, ACES 2.402

Design for Manufacturability: Embeddable Test Structures for Measuring Process Variations and Assessing DFM Practices

 Techniques to improve Design for Manufacturability (DFM) has been around for a long time, e.g. a technology’s design rules represent an early form of DFM. However, when technology was scaled to 180 nm — a feature size smaller than the wavelength of the light source used in photolithography (193 nm) — sub-resolution printability issues became a major concern. Reticle enhancement techniques, such as optical proximity correction, phase shift masking and off-axis illumination, were introduced to improve printability and have enjoyed a great deal of success.However, these techniques have become increasingly less effective as technologies scaled to and below 45 nm, resulting in higher levels of both random and systematic process variations and in the more frequent occurrence of systematic defects. In my presentation, I will describe structured “circuit context”-oriented techniques that are designed to measure the impact of random and systematic process variations, such as those that introduce variations in metal resistance and leakage, and will present data collected from ICs fabricated in IBM’s 65 nm SOI process. The proposed test structures and techniques are designed to provide regional, layout-oriented information about these variations across the 3-D topology of the IC. I will also describe an embeddable test structure for measuring the delay variations introduced by SOI history effect. Time permitting, I will discuss our proposed test structures and infrastructures that are designed to assess the impact of various DFM practices on functional and parametric yield.

Professor Brian Evans
ECE Department, UT Austin
October 7, 2009, 5pm, ENS 637

Radio Frequency Interference Sensing and Mitigation in Wireless Receivers
Radio frequency interference (RFI) is a key limiting factor in communication performance of Wi-Fi, WiMax, cellular, and other wireless data communication systems. Sources of RFI include (1) other wireless users/services operating in the same frequency band, a.k.a. co-channel interference, (2) nearby electronic equipment, such as microwave ovens radiating in the 2.4 GHz band, and (3) the computational platform itself, including clock circuitry and power saving subsystems in laptops and notebooks. In this talk, we present statistical modeling of platform RFI, validate the models using measured platform RFI datasets, and propose receiver designs for mitigating platform RFI. Several proposed designs demonstrate 10x-100x reduction in bit error rate for single-antenna and two-antenna receivers. The statistical models for platform RFI also model co-channel interference, and can be generalized to model RFI from nearby electronic equipment.

ICSG is launching the ICS Seminar which combines the previously seperate VLSI Seminar Series and UT Mixed-Signal/RF Integrated Circuits Seminar Series.  The ICS Seminar’s goal is to provide an open forum for faculty, graduate students and local industry experts to share new ideas and directions in the general area of large-scale integrated circuits. The seminar talks cover a diverse set of research topics.

The first ICS Seminar talk is by Professor Brian Evans of UT ECE and is to be held on October 7 at 5pm in ENS637.