Welcome to the Integrated Circuits and Systems Group (ICSG) at the University of Texas at Austin
ICSG carries out research that spans all major areas of design and design methodology for digital, analog, mixed-signal, and RF CMOS ICs.
ICS Seminar: Prof. Gabriel Rebeiz, IEEE Solid-State-Circuit-Society Distinguished Lecturer
Room location: ACES 2.302
Date: April 18, 6:00 to 8:00 pm
Talk Abstract: This talk summarizes the recent work on phased arrays starting from the lower frequency chips at 6-12 GHz, and passing by the satellite communication chips at 6-22 GHz, and ending by the short-range communication chips and car radar chips at 60 GHz and 77-81 GHz. Different topologies will be covered: RF phase shifting, IF phase shifting, LO phase shifting, and and digital beamforming, with the pros and cons for each topology. Also, wafer-scale integration and the use of efficient on-chip antennas at 30 GHz and above will be presented. Phased-array systems from industry and academia will be covered in detail.
Biography: Prof. Gabriel Rebeiz is the Wireless Communications Industry Chair Professor at the University of California, San Diego. He is an IEEE Fellow, an NSF Presidential Young Investigator, an URSI Koga Gold Medal Recipient, IEEE MTT 2003 Distinguished Young Engineer, and is the recipient of the IEEE MTT 2000 Microwave Prize, the IEEE MTT 2010 Distinguished Educator Award and the IEEE Antennas and Propagation 2011 John D. Kraus Antenna Award. He is also the recipient of the 1998 Amoco Teaching Award given to the best undergraduate teacher at the University of Michigan, and the 2008 Jacobs ECE Teacher of the Year Award at UCSD. His group has lead the development of complex RFICs for phased array applications from X-band to W-band, culminating recently in wafer-scale integration with high efficiency on-chip antennas. His phased array work is now used by most companies developing complex communication and radar systems. He has graduated 50 PhD students and 16 post-doctoral fellows, and currently leads a group of 20 PhD students in mm-wave RFIC, planar mm-wave antennas and terahertz systems, microwave circuits, RF MEMS, tunable networks, and is the Director of the UCSD/DARPA Center on RF MEMS Reliability and Design Fundamentals.
ICS Seminar: Prof. Jiang Hu
Date and time: Thursday, April 12, 2013, 2-3 p.m.
Location: ACES 2.402
Talk Title:
Voltage Adaptation for Power-Efficient Integrated Circuits
Abstract:
As people cram more and more functions into IC chips, the chip power density quickly approaches its fundamental limit. Power has surpassed performance and become the number one concern in many chip designs, from mobile to server applications. This talk will present some recent works on how to improve chip power efficiency at both architectural level and circuit level. At the architectural level, the power challenge is compounded by the increasingly large demand for on-chip communication bandwidth and data storage capacity. I will show how to efficiently monitor the performance of on-chip network and shared cache in chip multiprocessors. Dynamic voltage and frequency scaling control techniques for the shared resources will be described. At the circuit level, variability is another challenge that exacerbates the power problem. This talk will introduce a couple of voltage adaptation techniques that aim to harness the variability challenge in a power-efficient manner.
Speaker Bio:
Jiang Hu received the B. S. degree in optical engineering from Zhejiang University, China, in 1990, the M. S. degree in physics in 1997, and the Ph. D. degree in electrical engineering from the University of Minnesota in 2001. He was with IBM Microelectronics from January 2001 to June 2002. Currently, he is an associate professor in the Department of Electrical and Computer Engineering at the Texas A&M University. His research interest is on Computer-Aided Design for VLSI circuits and systems, especially on large scale circuit optimization, clock network synthesis, robust design and on-chip communication. He received a best paper award at the ACM/IEEE Design Automation Conference in 2001, an IBM Invention Achievement Award in 2003 and a best paper award at the IEEE/ACM International Conference on Computer-Aided Design in 2011. He has served as technical program committee member for DAC, ICCAD, ISPD, ISQED, ICCD, DATE, ASPDAC, ISLPED and ISCAS, technical program chair and general chair for the ACM International Symposium on Physical Design, and associated editor for IEEE Transactions on CAD and ACM Transactions on Design Automation of Electronic Systems.
ICS Seminar: Prof. Steven M. Nowick
Date and time: Monday, April 1, 2013, 3-4 p.m.
Location: ACES 2.402
Talk Title:
Designing a Low-Power and Low-Latency Network-on-Chip Switch Architecture for Cost-Effective GALS Multicore Systems
Abstract:
There has been a resurgence of interest in asynchronous (i.e. clockless) digital design in recent years, as designers confront formidable challenges of high-speed clock distribution, chip complexity, power, design time, mixed-timing domains and reusability.
This talk is in two parts. First, I will give a brief overview of asynchronous and GALS (globally-asynchronous locally-synchronous) design, including a basic technical introduction and highlights of recent industry activity (Fulcrum Microsystems [now part of Intel], Boeing, Sun, Philips) and academia. I will also survey some of my key research areas: (i) robust mixed-timing interfaces, (ii) low-power delay-insensitive codes for global communication, and (iii) ultra-low energy systems (subthreshold/near-threshold).
In the second part, I will introduce our recent asynchronous switch design for very low-overhead GALS interconnection networks. Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems. However, they have found only limited applicability so far due to two main reasons: the lack of proper design tool flows as well as their significant area footprint over their synchronous counterparts. This talk proposes a largely unexplored design point for asynchronous NoCs, relying on transition-signaling (i.e. 2-phase handshaking) and single-rail bundled data encoding, which contributes to break the above barriers.
Compared to a leading lightweight synchronous switch architecture, “xpipesLite,” the post-layout asynchronous switch achieved a 71% area reduction, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit. A semi-automated CAD tool flow was developed, using Synopsys Design Compiler and IC Compiler.
This is joint work with Davide Bertozzi and Alberto Ghiribaldi (University of Ferrara, Italy).
Speaker Bio:
STEVEN M. NOWICK is a Professor of Computer Science and Electrical Engineering at Columbia University, and Chair of the Computer Engineering Program. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University. His main research area is on design methodologies and CAD tools for synthesis and optimization of asynchronous and mixed-timing digital systems. His current projects include: scalable networks-on-chip (NoC’s) for shared-memory parallel processors and embedded systems, ultra-low energy digital systems, and low-power and robust global communication.
Dr. Nowick is an IEEE Fellow (2009), and a recipient of an Alfred P. Sloan Research Fellowship (1995), and NSF CAREER (1995) and RIA (1993) Awards. He received Best Paper Awards at the International Conference on Computer Design (1991, 2012) and the IEEE Async Symposium (2000). He co-founded the IEEE “Async” Symposia series, and served as Program Committee Co-Chair (1994, 1999) and General Co-Chair (2005). He was Program Chair of the IEEE/ACM International Workshop on Logic and Synthesis (2002), and program track/subcommittee chair at DAC (2011-13), DATE (2009-10) and ICCD (2005). He is currently associate editor ACM Journal on Emerging Technologies in Computer Systems (JETC), and formerly associate editor of IEEE Transactions on CAD and IEEE Transactions on VLSI Systems. He is also currently the selection committee chair of the ACM/SIGDA Outstanding Dissertation in EDA (OPDA) Award (2012-13). He received the Columbia Engineering School (SEAS) Alumni Distinguished Faculty Teaching Award (2010). He holds 11 issued US patents.