Welcome to the Integrated Circuits and Systems Group (ICSG) at the University of Texas at Austin

ICSG carries out research that spans all major areas of design and design methodology for digital, analog, mixed-signal, and RF CMOS ICs.

ICS seminar: Prof. Howard Luong from HKUST

Posted on May 19, 2014

Time: May 30 (Friday), 6:15pm
Location: POB 2.402

Speaker: Howard C. Luong, Ph.D of Hong Kong University of Science and Technology

Topic: A Fully-Integrated CMOS Frequency Synthesizer for Software-Defined Radios

This talk presents the design and the measurements of a fully integrated frequency synthesizer for software-defined radios (SDRs), which meets both the frequency and the phase noise requirement for all the wireless standards from 47MHz to 10GHz, including the 14-band UWB, and the 802.15.3c standard from 57GHz to 66GHz. Implemented in a 0.13-m CMOS process, the synthesizer prototype occupies an active area of 3mm2, consumes a total power of 33mW to 83mW, and achieves a measured phase noise of -139.6dBc/Hz at 3MHz offset from a 1.7GHz carrier.

Biography: Howard Luong received his BS, MS, and PhD degrees in Electrical Engineering and Computer Sciences (EECS) from University of California at Berkeley in 1988, 1990, and 1994, respectively. Since September 1994, he has joined the EEE faculty at the Hong Kong University of Science and Technology where he is currently a professor. Professor Luong’s research interests are in analog, RF, and mm-Wave integrated circuits and systems for wireless and portable applications. He was a co-author of the two books entitled “Low-Voltage RF CMOS Frequency Synthesizers” published by Cambridge University Press in 2004 and “Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems” published by Kluwer Academic Publishers in 2003. Professor Luong is an IEEE Fellow. He is currently serving as an IEEE Solid-State Circuits Society Distinguished Lecturer, an Associate Editor for IEEE Virtual Journal on RFIC, and a technical program committee member of many conferences, including Custom Integrated Circuits Conference (CICC), European Solid-State Circuits Conference (ESSCIRC), and Asian Solid-State Circuits Conference (A-SSCC).

ICS Seminar: Prof. Aviral Shrivastava from ASU

Posted on February 26, 2014

Date and time: March 5, 4pm
Location: POB 2.402

Title: Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors

Abstract: Control Flow Checking (CFC) based techniques have gained a
reputation of providing effective, yet low-overhead protection from
soft errors. The basic idea is that if the control flow – or the
sequence of instructions that are executed – is correct, then most
probably the execution of the program is correct. Although researchers
claim the effectiveness of the proposed CFC techniques, we argue that
their evaluation has been inadequate and even wrong! Recently, the
metric of vulnerability has been proposed to quantify the
susceptibility of computation to soft errors. Laced with this
comprehensive metric, we quantitatively evaluate the effectiveness of
several existing CFC schemes, and obtain surprising results. Our
results show that existing CFC techniques are not only ineffective in
protecting from soft errors, but that they incur additional power and
performance overheads. Software-only CFC protection schemes (CFCSS
[21], CFCSS+NA [5], and CEDA [26]) increase system vulnerability by
18% to 21% with 17% to 38% performance overhead; hybrid CFC protection
technique, CFEDC [7] increases the vulnerability by 5%; while the
vulnerability remains almost the same for hardware only CFC protection
technique, CFCET [22], but they cause overheads of design cost, area,
and power due to the hardware modifications required for their
implementations.

Bio: Aviral Shrivastava is Associate Professor in the School of
Computing,Informatics and Decision Systems Engineering at the Arizona
State University, where he has established and heads the Compiler and
Microarchitecture Labs (CML). He received his Ph.D. and Masters in
Information and Computer Science from University of California,
Irvine, and bachelors in Computer Science and Engineering from Indian
Institute of Technology, Delhi. He is recipient of the 2011 NSF CAREER
Award, and 2012 Outstanding Junior Researcher in the School of
Computing, Informatics, and Decision Systems Engineering. His research
focuses in three important directions, 1. Manycore architectures and
compilers, 2. Programmable accelerators and compilers, and 3.
Quantitative Resilience. His research is funded by DOE, NSF and
several industries including Intel, Nvidia, Microsoft, Raytheon
Missile Systems, Samsung etc. He serves on organizing and program
committees of several premier embedded system conferences, including
DAC, ICCAD, ISLPED, CODES+ISSS, CASES and LCTES, and NSF and DOE
review panels.

ICS Seminar: Prof. Ayse Coskun from Boston University

Posted on February 3, 2014

Date: Feb. 10, 4-5pm
Location: ENS 314
Talk abstract:
Energy efficiency is a central issue in all computing domains. In data
centers, operational and cooling costs impose significant sustainability
challenges. In tandem, future processors are expected to run complex,
highly performance demanding workloads, making the well-studied energy
management policies inadequate. High power densities also increase the
on-chip temperatures and thermal variations, both of which degrade
system reliability and add to the system design complexity. Achieving
orders of magnitude of energy efficiency improvements requires novel
system and software design approaches coupled with dynamic techniques
that recognize the hardware-software characteristics and understand the
complex interplay among performance, energy, and temperature. This talk
will discuss two closely-tied research thrusts: (1) designing novel 3D
stacked architectures and the necessary runtime management strategies
for improving processor energy efficiency; and (2) developing workload
management and power regulation methods in data centers to reduce the
overall energy cost of computing.
Speaker Bio:
Ayse K. Coskun is an assistant professor in the Electrical and Computer
Engineering Department at Boston University. She received her MS and PhD
degrees in Computer Science and Engineering from University of
California, San Diego. Coskun’s research interests are temperature and
energy management, 3D stack architectures, computer architecture,
embedded systems, and data center energy efficiency. Prof. Coskun worked
at Sun Microsystems (now Oracle), San Diego prior to her current
position at BU. She received the best paper award at IFIP/IEEE VLSI-SoC
Conference in 2009 and at High Performance Embedded Computing (HPEC)
Workshop in 2011, and she is a recipient of the NSF CAREER award. She
has served as an associate editor for ACM Transactions on Design
Automation of Electronic Systems and IEEE Embedded Systems Letters.
Coskun also writes a bi-monthly column on green computing for Circuit
Cellar magazine.

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